Analysis & Synthesis report for mux21
Tue Nov 14 14:40:16 2006
Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. General Register Statistics
  8. Analysis & Synthesis Equations
  9. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+----------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                               ;
+-----------------------------+----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Nov 14 14:40:16 2006        ;
; Quartus II Version          ; 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition ;
; Revision Name               ; mux21                                        ;
; Top-level Entity Name       ; MUX21                                        ;
; Family                      ; FLEX10K                                      ;
; Total logic elements        ; 1                                            ;
; Total pins                  ; 4                                            ;
; Total memory bits           ; 0                                            ;
+-----------------------------+----------------------------------------------+


+----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                ;
+------------------------------------------------------------+-----------------+---------------+
; Option                                                     ; Setting         ; Default Value ;
+------------------------------------------------------------+-----------------+---------------+
; Device                                                     ; EPF10K70RC240-4 ;               ;
; Top-level entity name                                      ; mux21           ; mux21         ;
; Family name                                                ; FLEX10K         ; Stratix       ;
; Use smart compilation                                      ; Off             ; Off           ;
; Create Debugging Nodes for IP Cores                        ; off             ; off           ;
; Preserve fewer node names                                  ; On              ; On            ;
; Disable OpenCore Plus hardware evaluation                  ; Off             ; Off           ;
; Verilog Version                                            ; Verilog_2001    ; Verilog_2001  ;
; VHDL Version                                               ; VHDL93          ; VHDL93        ;
; State Machine Processing                                   ; Auto            ; Auto          ;
; Extract Verilog State Machines                             ; On              ; On            ;
; Extract VHDL State Machines                                ; On              ; On            ;
; Add Pass-Through Logic to Inferred RAMs                    ; On              ; On            ;
; NOT Gate Push-Back                                         ; On              ; On            ;
; Power-Up Don't Care                                        ; On              ; On            ;
; Remove Redundant Logic Cells                               ; Off             ; Off           ;
; Remove Duplicate Registers                                 ; On              ; On            ;
; Ignore CARRY Buffers                                       ; Off             ; Off           ;
; Ignore CASCADE Buffers                                     ; Off             ; Off           ;
; Ignore GLOBAL Buffers                                      ; Off             ; Off           ;
; Ignore ROW GLOBAL Buffers                                  ; Off             ; Off           ;
; Ignore LCELL Buffers                                       ; Off             ; Off           ;
; Ignore SOFT Buffers                                        ; On              ; On            ;
; Limit AHDL Integers to 32 Bits                             ; Off             ; Off           ;
; Auto Implement in ROM                                      ; Off             ; Off           ;
; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K       ; Area            ; Area          ;
; Carry Chain Length -- FLEX 10K                             ; 32              ; 32            ;
; Cascade Chain Length                                       ; 2               ; 2             ;
; Auto Carry Chains                                          ; On              ; On            ;
; Auto Open-Drain Pins                                       ; On              ; On            ;
; Remove Duplicate Logic                                     ; On              ; On            ;
; Auto ROM Replacement                                       ; On              ; On            ;
; Auto RAM Replacement                                       ; On              ; On            ;
; Auto Clock Enable Replacement                              ; On              ; On            ;
; Auto Resource Sharing                                      ; Off             ; Off           ;
; Allow Any RAM Size For Recognition                         ; Off             ; Off           ;
; Allow Any ROM Size For Recognition                         ; Off             ; Off           ;
; Ignore translate_off and translate_on Synthesis Directives ; Off             ; Off           ;
; Show Parameter Settings Tables in Synthesis Report         ; On              ; On            ;
+------------------------------------------------------------+-----------------+---------------+


+------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                           ;
+----------------------------------+-----------------+-----------------+-------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path              ;
+----------------------------------+-----------------+-----------------+-------------------------------------------+
; mux21.vhd                        ; yes             ; User VHDL File  ; E:/Faculdade/Lógicos/Lab/Prova3/mux21.vhd ;
+----------------------------------+-----------------+-----------------+-------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------+-----------+
; Resource                        ; Usage     ;
+---------------------------------+-----------+
; Total logic elements            ; 1         ;
; Total combinational functions   ; 1         ;
;     -- Total 4-input functions  ; 0         ;
;     -- Total 3-input functions  ; 1         ;
;     -- Total 2-input functions  ; 0         ;
;     -- Total 1-input functions  ; 0         ;
;     -- Total 0-input functions  ; 0         ;
; Combinational cells for routing ; 0         ;
; Total registers                 ; 0         ;
; I/O pins                        ; 4         ;
; Maximum fan-out node            ; f~4       ;
; Maximum fan-out                 ; 1         ;
; Total fan-out                   ; 4         ;
; Average fan-out                 ; 0.80      ;
+---------------------------------+-----------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                        ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+---------------------+
; |MUX21                     ; 1 (1)       ; 0            ; 0           ; 4    ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |MUX21              ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/Faculdade/Lógicos/Lab/Prova3/mux21.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Web Edition
    Info: Processing started: Tue Nov 14 14:40:04 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mux21 -c mux21
Info: Found 2 design units, including 1 entities, in source file mux21.vhd
    Info: Found design unit 1: MUX21-behavior
    Info: Found entity 1: MUX21
Info: Found 2 design units, including 1 entities, in source file mux2.vhd
    Info: Found design unit 1: mux2-logicfunc
    Info: Found entity 1: mux2
Info: Elaborating entity "mux21" for the top level hierarchy
Info: Implemented 5 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 1 output pins
    Info: Implemented 1 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Tue Nov 14 14:40:16 2006
    Info: Elapsed time: 00:00:13


